Reconfigurable phase-locked loops on a FPGA utilizing intrinsic synchronizability

Hisa-Aki Tanaka, Akio Hasegawa, and Shinichiro Haruyama
IEE Electronics Letters, 2001.


A new digital phase-locked loop (PLL), utilising the synchronisability of electrical oscillators, on a field-programmable gate array has been developed. By interconnecting such PLLs, a dynanlicaly reconflgurable clock network was fonncd, which has been difficult with conventional PLL techniques.

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